Introduction to Plasma Damage

Introduction to Plasma Damage

Introduction to Plasma Damage

Semiconductor devices are well known to be sensitive to process conditions, and achieving optimum performance requires an understanding of the issues associated with damage. Critical processes in fabricating devices involve plasma. They provide unique capabilities such as dry etching extremely high-resolution patterns and plasma-enhanced deposition approaches used to reduce thermal loads and provide very thin layers. As we continue to push device performance and physics, it is important to better understand plasma processes’ role as they relate to damage. 

How is damage manifested?

Device damage from plasma processing is a very real phenomenon. We can look at the final device and compare it to the expected performance, or we can use test structures to explore a specific material property. A few examples include changes to mobility and carrier concentration in HEMT devices, changes to threshold voltages for laser and diodes, and the creation of current leakage paths in LEDs. 

The process cycle for building a device can take a long time and involve costly materials, so surrogate materials are often used in conjunction with a wide range of analytical techniques. These techniques include photoluminescence, DLTS, Hall measurements, Schottky barriers, diode ideality, Raman and ellipsometry spectroscopy, breakdown voltages, and contact resistance as well as other techniques that do surface analysis (e.g. XPS, SIMS). Unfortunately, such methods often take specialized equipment, and interpretation can be complicated.

How do we explore the damage mechanisms? 

Plasma environments are complex and offer many different mechanisms for inducing damage. The amount of damage that is tolerable depends on the device. A feature such as a 2-DEG that is near the surface may be significantly more sensitive than a 2-DEG that is located farther from the surface. Similarly, a wide feature may be relatively immune to sidewall damage while a narrow feature may be greatly impacted. We can group the sources into categories and the damage they inflict as follows:

  • Ion bombardment: Ions accelerated across plasma sheaths can be on the order of 10s to 100s eV. At these energies, a wide range of effects can be observed and can be attributed to lattice displacement generating traps, interlayer mixing, surface damage (surface states and changes in chemical reactivity), and implantation. Depending on the material and the ion energies the depth of material affected can range from a few nanometers to a few hundred nanometers. The important parameters are total flux, ion energies, and ion masses.

As devices have moved from primarily planar structures to three-dimensional structures (e.g. FinFETS, VCSELs, μLEDs, waveguides) there is concern about sidewall damage. In general, due to the highly directional nature of the ions and their predominantly normal trajectory to the substrate, they contribute little damage to sidewalls. “Little” is a relative term, and it depends on the device. With three dimensional structures in the nano regime, even a few 10s of angstroms of damage can have significant effects. Often the expectations that a bias of < 50 E generates acceptable damage levels, but this is very generic guidance.

  • Electrostatics (charging and arcing): The charged plasma species, electrons, and ions, in combination with insulators, can induce local electrostatic fields. The local fields that develop can deflect of shade incoming ions causing changes in the profiles (bowing and notching). This build-up of charge in thin dielectrics can also allow current flow during discharge which can cause traps to be generated. In some structures, the problem can be severe enough to cause arcing between features. Since this second problem occurs with thin dielectrics, it can be observed near the end of etching when the dielectric is thin or during the initial states of deposition in HDPCVD. The phenomenon may affect electric field breakdown of dielectrics.

  • Radiation: Vacuum UV is characterized by radiation with a wavelength of less than 200 nm (>6.2 eV). Radiation at these energies can be absorbed and create energetic electron hole pairs. In dielectrics this process can ultimately generate a trapped charge, surface damage, or an interface defects. At sufficiently high intensities (high plasma densities) this process can induce dielectric conductivity and the potential for more damage. Due to the high energy nature of the radiation, the depth of absorption is small, and this helps in limiting the damage.
  • Contamination: Multiple sources can contribute to contamination and include resputtering from the mask, redeposition from the chamber surfaces, and most commonly from the plasma chemistry itself. An example of contamination is etching with fluorocarbons. Fluorocarbons readily form polymers and thorough cleaning is often required to remove all traces. Other chemistries form polymers as well such as methane/hydrogen processes.

How can we minimize the induced damage?

First, it is important to recognize that not all applications are affected by damage, and one must make an assessment whether focus on damage is necessary. When damage is an issue there are ways to minimize the effects. Obviously, from a device design perspective, understating how a device may be affected is important.

If one can locate the sensitive parts of a device away from the plasma it will help (e.g. locating a 2-DEG farther from the surface). It will help significantly if the bias can be reduced, and the ion flux reduced with a lower power plasma. This is a key motivation for remote or downstream plasma technologies to be used when possible (such as with photoresist stripping). Perhaps counterintuitively, it helps to have fast etch rates (hopefully without high bias) so that the desired etch depth can be achieved in the minimum time. As mentioned, ion damage is primarily a function of flux and ion energies. With a faster etching rate, the damage has less time to accumulate. It makes sense that an accurate endpoint would also help avoid unnecessary over-etching.

Sidewall damage from ions bombardment, while typically minimal, can still be important. The typically off-axis ion trajectory is limited to ~5 degrees off normal for a collision-free transit through the plasma sheath. Increasing the pressure will cause more scattering and a larger angle but reduce the ion energy. Depending on the specifics of the application, it is difficult to predict which effect will dominate.

As ions play such an important role that many new approaches have been and are being developed. These approaches include ion filters, different rf frequencies, pulsing, and plasma density leveling to avoid charging.

Can we reverse or remove the damage?

As always with process-related questions, the answer starts with “it depends”. It depends on the damage that has been inflicted. Often, ion induced damage can be repaired with anneals. This is very specific to the material and the application. Many applications will not tolerate the high temperatures required to restore the material properties. When anneals are not possible, wet etching or perhaps a downstream dry etching approach may be able to remove a thin damaged layer. Again, this is very material and application specific.


Often, due to the complicated issues surrounding damage, the request from customers is “no” or “zero” damage. This is followed by a discussion of what damage is of concern and critically how that damage might be measured. Unfortunately, one cannot simply baseline the zero damage case, and then make comparisons.

Up to this point, we have considered damage as some change to the material. However, there are other phenomena such as surface morphology that greatly affect a device’s performance. There might be more than one damage mechanism involved, and there might have to be a trade-off between different damage consequences. For example, a fast etch rate that reduces ion bombardment damage might also contribute to a rougher surface with more surface states. We have mentioned sidewall damage in the context of ion bombardment, but there is also the consideration of sidewall roughness. This may be the result of a poor mask or the etch chemistry that is used. Unfortunately, there are no easy answers.

Detecting damage is not trivial, and many creative approaches have been used to better understand the issues. Although plasma induced damage is a complicated topic, there are many applications where damage is not an issue. That is called ending on an upbeat note.

To learn more, download our whitepaper comparing Plasma Etching technology: PE, RIE, and ICP-RIE.

Acronym list

DLTS- Deep Level Transient Spectroscopy

HEMT – High Electron Mobility Transistor

2-DEG – Two Dimensional Electron Gas

HDPCVD – High Density Plasma Chemical Vapor Deposition

VCSEL – Vertical Cavity Surface Emitting Laser

μLED – micro Light Emitting Diode

FinFET – Fin Field Effect Transistor

XPS – X-ray Photoelectron Spectroscopy

SIMS – Secondary Ion Mass Spectroscopy

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